Then you didn‘t look close enough...
It is in the service manual, but instead of traditional analog signal routing, all is handled in digital serial data by 2 Xilinx XC9572XL logic arrays and 2 asynchronous sample rate converters for input and output.
Of course you can‘t peek inside the logic arrays, but if you translate the abbreviated labels of the connectors to something meaningful, you may get an idea what‘s going on.
A good approach would be to print an enlarged version and draw with color markers over lines of interest. In b/w it‘s almost impossible to visually keep track.
(or use it as a layer in some CAD software)
But it‘s a very, very complex endeavor ... tbh I don‘t understand half of it
The PC IO Block Diagram is a good starting point before going into circuit details.
Imho the doc is sufficient to maintain/service the unit, but few room for optimization.
At least Jim Williams (a well respected circuit designer/modder) once mentioned it‘s too complex for reasonable „improvements“ (when asked about suggestions).