Hi all,
I'm new here, so I just wanted to say hi to everyone. I am a new owner of an MPC 1000. I was researching the memory upgrade, and I had some questions. Now please don't get mad, I have valid reasons for asking these questions, mostly because the answers that have been given have not been proven to me to be true. So anyhow,
1) The memory upgrade that is supplied by Akai, which uses the hy57v561620bt-h Hynix DRAM. Does it have DRAM chips on both sides? I only see two in any pictures that I have seen, because those pictures only show one side. Since this is a 128M SODIMM, and those chips are 16Mx16 DRAM, (which equates to 32MB per chip), it doesn't add up that it would only have two chips on it. It should have a total of 4, so I am asking for someone to confirm or deny this.
2) I know that everyone says that the MPC cannot read both sides of the SODIMM. But the only reason anyone has ever given that that is so is either conjecture, or an assumption based on the fact that when they put memory in it only sees half the memory. Does anyone have any valid arguments as to why the statement that 'It only reads one side' is true? Proof?
The reason I am digging so hard is because I have a theory. Is it possible the reason that every SODIMM that has been tried in the MPC has only produced half the size is due to the fact that that SODIMM was using a DRAM chip that was too high in density. This would produce the 'half the memory' effect.
For example, an 256MB SODIMM using a configuration of 16 chips of 16Mx8 (8 chips per side), such as the Kingston KTM-TP390X/256, or using 8 chips of 16Mx16 (4 chips per side) would, if my theory is correct, allow the MPC to read 256MB. Any 16 chip 256MB SODIMM should be low-density of 16Mb per DRAM.
If you stuck a normal, cheap, high-density SODIMM in there, which used 16 chips of 32Mx4 (8 chips per side), or 8 chips of 32Mx8 (4 chips per side), the density (32M) per chip would be higher than the MPC could handle, which I am assuming in my theory is 16Mb per chip. This would cause half the memory (or only 16Mb per chip) to be read, resulting in 128MB.
The other interesting angle is that if indeed the MPC can only read one side of the SODIMM, it may still be possible to use a low density DRAM configuration to procure more than 128MB on one SODIMM. It is possible to find a 16Mx16 based 512MB SODIMM, which would then be using 16 chips, 8 per side. This would be a workable 256MB within the confines of only 'one side', and would also remain low enough density to be read by a controller expecting a max of 16Mb DRAM density. Granted, such a SODIMM will likely not be very easy to find, but they exist. The rule of 16 chips I gave above for 256MB SODIMMs would not apply with 512MB, as both low and high density can be found with 16 chips.
Thoughts? Please disprove me so I don't waste my money

Alex